Recently, many device manufacturers are using damascene interconnect systems for the fabrication of integrated circuit devices. Contrary to the fabrication method of Al-alloy-based interconnects that comprises the deposition of Al-based alloy layer and plasma etch (i.e., reactive ion etch, dry etch or patterning etch) of it, the damascene counterpart comprises filling a damascene opening (i.e., a damascene feature) with a conductor. In typical damascene processes, copper (Cu) is used to fill the damascene feature as a conductor.
Although the damascene process has been used in the microelectronic industry for many years, various problems of IC device performance, reliability, yield and throughput have been reported in prior art damascene process cases. Ever-shrinking integrated circuit dimension makes the problems more pronounced.
Many of such problems found in the prior art damascene processes are closely related to the contamination and the damage caused by the prior art damascene processes to the materials constituting a damascene interconnect system, such as an interlevel dielectric (ILD) layer, conductors, and conductive liner layers. Many other unique problems of each damascene process will be explained as well in the following.
When a fabrication process of a contact opening, such as a via hole that is formed for the fabrication of both single and dual damascene interconnect systems exposes the conductor formed in a substrate at the bottom of the contact opening (in other words, ‘at the contact opening bottom’ and ‘at the via bottom’), the material damage and the contamination may occur. Depending on the context, the phrase of “at the via bottom” may have a meaning of “at a location on the bottom side of a via or via hole” or “at a location beneath a via bottom or a via hole bottom,” The conductor formed in a substrate is referred as a lower level conductor as well.
The first process that exposes the conductor may be the barrier open process (i.e., via open process) of the prior art damascene-feature-forming processes, wherein the conductor formed in a substrate is exposed to reactive and energetic environments when the last portion of a dielectric layer, such as the last portion of the via etch stop layer (via ESL) deposited over the conductor is etched through at the bottom of a via hole (in other word, ‘at the via bottom’).
Note that damascene features including those fabricated by the present invention, such as a single damascene contact hole and a dual damascene feature comprising a trench and a via hole, are generally formed by a damascene-feature-forming process within a dielectric layer deposited over a substrate that has the lower level conductor. By filling the damascene features with a conductor that is either identical to or different from that included in the substrate, various damascene interconnect systems can be fabricated. Both the conductor that is filling the damascene features and the conductor that is formed in the substrate can be fabricated with any kind of electrically conductive material. Usually, however, they comprise at least one material selected from a group comprising carbon, pure metal materials such as copper and tungsten, metal alloys such as copper alloys and aluminum alloys, metal silicides such as nickel silicide, metal oxides such as tin dioxide, metal nitrides such as tantalum nitride, metal carbides such as TaC, metal borides such as TiB2, metal carbonitrides such as TaCN, and doped silicons.
The contact hole and the via hole are related. The term “hole” and the term “opening” are inter-changeable with each other. The substrate may be a silicon (Si) wafer or a glass sheet, or other material body, such as a GaAs wafer. The substrate may include other components than the conductor, such as semiconductor components, e.g., a transistor. The dielectric layer comprises either a single dielectric material layer or a composite of multiple dielectric layers. The composite of multiple dielectric layers comprises one or more interlevel dielectric (ILD) layers and one or more other dielectric layers than the ILD layers. Each of the ILD layers may comprise a silicon dioxide or a material layer whose dielectric constant is lower than that of the silicon dioxide. Each of the aforementioned other dielectric layers has one or more functions selected from a group comprising functions of a capping layer, a dielectric diffusion barrier layer, a passivation layer, a chemical mechanical polishing (CMP) stop layer, and an etch stop layer (ESL) such as a via etch stop layer (via ESL) and a trench etch stop layer (trench ESL).
FIG. 1 shows an exemplary dual damascene feature whose via ESL 105 has been removed completely at the bottom of the via (via bottom) so that the top surface 127 of the uppermost conductor, Mx 101 formed within a substrate (i.e., lower level conductor) is exposed after a barrier open process. The damascene feature comprises a trench 119 and a contact opening (i.e., via hole 117) that are formed within a dielectric layer comprising ILD layers 107, 111, and other dielectric layers 105, 109, 113 than the ILD layers. In this disclosure, the other dielectric layers 105, 109 and 113 are named as a via ESL, trench ESL, and CMP stop layer, respectively. The top surface of the trench ESL 109 constitutes a trench bottom 123, and that of the CMP stop layer 113, a field area 114. Each of the other dielectric layers may have other function or functions than that implied by its name, as aforementioned. This damascene feature that has no dielectric layer retained at the via bottom is used for the fabrication of prior art dual damascene interconnect systems each of which has either an embedded via or a planar via. Note that the damascene feature shown in FIG. 1 can also be used as a preliminary damascene feature in an embodiment of the present invention as will be explained. In this disclosure, a preliminary damascene feature is a damascene opening, such as a single contact hole and a dual damascene opening that comprises a contact hole, over which a sacrificial layer is deposited prior to exposing a conductor formed in a substrate at the contact hole bottom. Each of the aforementioned dielectric layers 105, 107, 109, 111, 113 can be either a single material layer or a composite of multiple material layers.
Since the thorough removal of the via ESL at the via bottom during the barrier open process is a necessity for the formation of the prior art damascene interconnect systems having either a planar via or an embedded via, the top layer of the conductor Mx 101 can be etched away unintentionally, and recessed as illustrated in FIG. 1 (see location 127) during the barrier open process.
Problem 1) ILD contamination by conductor materials: If the conductor are etched by the barrier open process, the ILD layers 107, 111 can be contaminated by the materials constituting the conductor Mx 101 since the conductor materials, such as copper (Cu) can be subsequently re-deposited as a form of conductor-material-rich post etch residue (PER) on the surface of the ILD layers (e.g., 121 and 125). If the conductor is Cu, it can diffuse fast into the ILD materials, causing IC reliability problems such as dielectric breakdown. Even if the conductor comprised other metals than Cu, their migration to the ILD layers may cause similar problems.
Problem 2) Contamination and damage by halogen- and hydrogen-containing chemistries: Next, the surface 127 and the inner portion 115 of the conductor, Mx may be contaminated by halogen atoms during a barrier open process, if a halogen-containing chemistry are used. If this happened on the surface of a Cu conductor, Cu halides that cannot be removed via a thermally driven evaporation mechanism would form, adversely influencing the performance and reliability of the damascene interconnect system. Although a plasma of reducing chemistries, such as hydrogen plasma and NH3 plasma, can remove halogen atoms from the Cu halides during a pre-clean process before the deposition of a conductive liner layer, hydrogen-related problems, such as Cu hydride and Cu hydroxyl impurity formation, can be caused to the conductor. Since the ILD layers are exposed to the chemistry of the pre-clean process, any hydrogen-containing plasma chemistry can cause problems to ILD layers, especially to those consisting of low K dielectrics, such as Flare™, SiLK™ and carbon-doped silicate glasses.
Problem 3) Limited choices for barrier open process chemistry for prior art damascene-feature-forming process: Another type of damage that can happen to the conductor (e.g., Mx) at the via bottom might be its oxidation during the barrier open process if an oxygen-containing plasma chemistry were used. This is because the barrier open process exposes the conductor to its chemistry in the prior art damascene process scheme. Therefore, an oxidizing chemistry cannot be used for the barrier open process during the prior art damascene-feature-forming process, even though it might provide various advantageous merits, such as good feature profile controllability and high etching speed.
Problem 4) Difficulties in removing the persistent PER: Yet another problem caused by the complete via ESL removal that is accompanied by the unintentional etch back of the conductor materials during the barrier open process, may be the difficulty in removing very persistent metal-rich post etch residues (PERs), such as organometallic polymer residue (i.e., hydrocarbon-based polymer containing the elements of Mx) by using a wet clean chemistry without causing further problems, such as undercut, ILD lift-off, critical dimension loss (CD loss), conductor corrosion, and organic metal formation. Exposing conductor during a damascene-feature-forming process is thus responsible for a slow, complicated and costly wet clean process, degraded device performance, undesirable feature profile, poor device reliability, low throughput, and decreased device yield.
The cause of the problems listed above is rooted in the fact that the last layer of the dielectric layer, such as the via ESL is completely removed during the conventional barrier open process step. In order to mitigate the problems, via open processes have been performed carefully during prior art damascene-feature-forming processes so as to suppress the etch back of the conductor. However, it is close to impossible to remove the dielectric layer completely without etching back the conductor (e.g., Mx) at all. Providing a viable damascene-feature-forming process that can prevent or mitigate the aforementioned problems is within the scope of the present invention.
Following are further problems of prior art damascene processes in addition to those caused by the prior art damascene-feature-forming process. In a prior art damascene process, damascene features, such as the one shown in FIG. 1 are then provided to subsequent process steps for fabricating a via alone in a single damascene via fabrication case, or a via and an one-level upper interconnect line than the conductor formed in a substrate in a case of fabricating a dual damascene interconnect system.
A via formed by a prior art damascene process can be classified either as a planar via or an embedded via. The prior art planar via has been formed while avoiding the removal of underlying conductor materials intentionally in any step of a damascene process. Note that a planar via formed by a prior art damascene process might be unintentionally embedded in the conductor of the substrate a little due to the inevitable etch back of the conductor during the conventional damascene-feature-forming process as aforementioned.
Refer to FIG. 2A for an exemplary prior art dual damascene interconnect system comprising a planar via (Vx 203a), and a next level (in other words, an upper level) conductor (Mx+1 201) both of which are covered by a conductive liner layer (i.e., 205), and formed over a conductor Mx 101 that is formed in a substrate. The damascene process steps for fabricating this damascene interconnect system, however, can cause a multitude of problems as listed below.
Problem 5) Limited options for pre-clean processes, and their inefficiency: Typically, a gentle hydrogen-plasma-based pre-clean process has been performed prior to the deposition of the conductive liner layer 205 to remove the contaminants from the top surface of the conductor at the bottom of the via 203a (via bottom). This is because any intensive process, such as an argon (Ar) sputtering, may cause serious problems related to the contamination to the damascene feature surface by sputtered conductor materials, such as Cu. This means that the surface of the conductor at the via bottom may not be cleaned sufficiently prior to the deposition of a conductive liner layer due to the limited choices. Ever-decreasing critical dimension of the damascene feature can exacerbate the problem of the pre-clean process. Also, any prolonged hydrogen-plasma-based pre-clean process can damage ILD materials, such as Flare™ and SiLK™, and can enlarge critical dimensions (CDs) of damascene features, such as trench width and via diameter.
Problem 6) Poor electrical and mechanical property of a planar via: Since no further removal of contaminated and damaged material from the top surface of the conductor at the bottom of the planar via 203a is performed after the pre-clean process in the damascene process scheme used for fabricating a damascene interconnect system having a planar via (i.e., damascene process for fabricating a planar via), any contamination or damage that has not been removed by the pre-clean process can be trapped along the border line 207 between the conductive liner layer 205 and the underlying conductor 101 shown in FIG. 2A, and cause electrical problems, such as a high via resistance, and thermo-mechanical problem, such as via pull back. The significant thermal and mechanical stress caused by the damascene process may exacerbate these problems.
Problem 7) Problem of planar via disconnection due to void formation: Another problem arises when a void is formed in the via (not shown) or in the underlying conductor (see FIG. 2B) due to various reasons, such as Cu electromigration (EM). As shown in FIG. 2B, if the conductor Mx 101 had a void 209 whose size is large enough to disconnect the via 203a from the Mx, the planar via is no longer able to carry sufficient electrical current from Mx 101 to Mx+1 201, or from Mx+1 201 to Mx 101. As the number of the unlanded vias such as that shown in FIG. 2B increases in a die with decreasing feature size, the disconnection problem of the planar via worsens.
Problem 8) Problem of low yield and high production cost of a planar via: Furthermore, due to the aforementioned problems, the damascene process for fabricating an interconnect system having a planar via may suffer a low production yield, which is the largest contributor to a high production cost.
An ideally fabricated embedded via can remove the aforementioned problems related to the planar via (see FIG. 2C and FIG. 2 D for an ideally fabricated embedded via). The ideally fabricated embedded via is a via formed by an ideal damascene process that does not cause damage or contamination to the materials constituting the damascene interconnect system having the embedded via. Forming the ideally fabricated embedded via is within the scope of the present invention.
Since any damaged and contaminated material existing at the via bottom area along the border line 207 between the conductive liner layer 205 and the underlying conductor 101 shown in FIG. 2A is physically removed during the formation of the ideally embedded via, the aforementioned problem of poor electrical performance can be removed. Also, extending the tip 211 of via 203b into Mx to embed it in the Mx three dimensionally can significantly reduce the mechanical vulnerability of a via, compared to the planar via that is contacting underlying conductor two dimensionally. Furthermore, even if there is a large void 213 (provide that its size is the same as that of the void 209 shown in FIG. 2B) in the via or in the conductor (not shown), the embedded via is still able to carry electrical current, as illustrated in FIG. 2D, thus improving the reliability of integrated circuit devices. Moreover, the area for electrical conduction 215 of a planar via can be severely reduced if it is unlanded as depicted in FIG. 2E. By embedding a via, the area for the electrical conduction 217 can be enlarged, as described in FIG. 2F.
However, forming an ideally embedded via by using a prior art damascene process used for the embedded via formation may be difficult. One of the many reasons is that the prior art embedded via formation process, which is also called as a punch-through process comprises an etch back of already-deposited conductive liner layer at the via bottom, together with the conductor formed in the substrate, causing contamination and damage to the materials that constitute a damascene interconnect system. In addition to the damage and contamination problems, the prior art damascene process has other intrinsic problems.
FIG. 3A through FIG. 3D show steps that are carrier out in an exemplary damascene process selected to explain possible damages and contaminations related to prior art damascene processes used for the formation of an embedded via. In the exemplary process, the conductive liner layer comprising a conductive diffusion barrier layer and an adhesion layer is deposited by a sputtering method, which is a widely used PVD method for the manufacture of the prior art damascene interconnect system. Even if the exemplary process explained in FIG. 3A through FIG. 3D might be slightly different in its details from the prior art processes used in the industry, many of its process steps are implemented in the prior art processes.
FIG. 3A shows an as-deposited conductive diffusion barrier 311 that was deposited by the sputtering method on an unlanded via pattern. The sputtering method often forms overhang structures such as 305 and 309 at the entrance of the via hole 117, and that of the trench 119, respectively, together with a thick barrier material deposit 301 at the via bottom. The overhang structures often cause thin diffusion barrier on the via bottom sidewall 303 and that on the trench bottom sidewall 307 that would in turn cause Cu diffusion through them. The large volume occupied by the overhanging conductive diffusion barrier material 305 and 309, and the thick conductive diffusion barrier material 301 at the via bottom can cause a problem of high interconnect resistance.
To solve the various problems originated from the intrinsically poor conformality of the sputter-deposited conductive diffusion barrier layer and to form a recess in the underlying conductor for the formation of an embedded via, an intensive etch back process has been performed during or after, or during and after the deposition of the conductive liner layer in the prior art damascene processes. It has been expected that by the intensive etch back process, the thick conductive liner layer material at location 305, 309 and 301 are etched back, and the materials etched back (re-sputtered) are redistributed to reinforce the thin conductive diffusion barrier layer 303 and 307.
However, this intensive etch back of growing or already-grown conductive liner layer for the formation of embedded via through forming a recess in a conductor at the via bottom can cause various grave problems as illustrated in FIG. 3B.
Problem 9) Integrity loss of materials involved due to physical damage: The intensive etch back process can harm the integrity of the conductive diffusion barrier layer by bombarding it heavily on a wide scale. Also, the intensive etch back process can locally cause the formation of micro-trenches at thin spots such as the trench bottom corner 323a and via bottom corner 323b, 323c, due to one or more reasons, such as unevenly distributed electrical charges along the materials' surface, concentrated ion flux reflected by the overhangs and then directed toward the bottom corners of the via and the trench, and overly formed bias voltage on the substrate. The depth of the micro-trench 323c, for example, in the substrate dielectric layer 103 can become large if the resistance of the material constituting the dielectric layer 103 against the re-sputtering is significantly weaker than that of the conductive diffusion barrier material. Once formed, these micro-trenches can cause Cu diffusion through them to the dielectric layers 103 and 107. Since they are usually too narrow and too deep, subsequently deposited material layer by the sputter method, such as the adhesion layer 331 (see FIG. 3C), may not be able to seal them conformally. Depositing a thick adhesion layer that also functions as a conductive diffusion barrier layer, such as tantalum and TaNx (0<x≦0.1), in an attempt to seal the micro-trench would increase the resistance of the whole interconnect system.
Problem 10) Contamination by etched back materials: The second problem of the intensive etch back process for forming a recess in the conductor may be the integrity loss of the conductive diffusion barrier layer due to the contamination caused by the byproduct materials of the etch back process. Since this etch back process is done during or after, or during and after the deposition of the conductive diffusion barrier, this barrier surface can be re-deposited with the byproduct of the etch back process (e.g., composite impurity particles 325 comprising the materials of the diffusion barrier 311, ILD layers 103 and 107, and the underlying conductor, Mx 101), as shown in FIG. 3B. If, for example, the conductor comprised Cu, the Cu atoms etched back from the conductor and re-deposited on the surface of the conductive diffusion barrier layer as a form of the impurity particle may be bombarded heavily by the energetic ions of the etch back process, and incorporated deeply into the conductive diffusion barrier layer. The deeply incorporated Cu atoms have a high chance to diffuse through the conductive diffusion barrier layer to the ILD layer. Under this situation, the property and the integrity of the ILD layer and the conductor can get deteriorated as well.
Problem 11) Faceting of trench and via entrance: Moreover, the intensive etch back process may cause faceting of the ILD at the trench entrance area 329 or at the via entrance area 326, or both. The diffusion barrier layer can also be faceted 327 at the trench entrance as shown in FIG. 3B. The faceting at the trench entrance 327, 329 can result in a decreased distance between neighboring interconnect lines, causing increased current leakage and signal interference between them. Also, the faceting at the via entrance can make neighboring vias (not shown in this figure) merge each other.
Problem 12) Non-uniform effect of the etch back process: A further problem of the etch back process performed over the sputter-deposited (PVD-grown) conductive diffusion barrier layer is the non-uniformity in its effects. More specifically, the effects of the etch back process, such as the depth of the recess formed into the conductor Mx 101, the severity of the micro-trench formation, and the degree of the faceting can change from feature to feature within a die on a substrate in an uncontrollable manner, as the aspect ratio of the damascene features, such as a via hole, varies. The most significant effect of the non-uniformity can be a severe yield drop of device production that is related to the recess depth non-uniformity. This is because, if the depth of a recess formed by the etch back process changes from via hole to via hole so that the conductive diffusion barrier layer is not punched through at the bottom of many via holes, the final vias formed in these via holes can show unallowably high via resistance for many reasons.
The significant non-uniformity in the effect of the etch back process is originated from a large variation in the topological characteristics of the sputter-deposited conductive diffusion barrier layer that is extremely sensitive to the change in the aspect ratio of the features in a die. Note that the topological characteristics, such as the overhang 305, 309 of the conductive diffusion barrier layer has a significant impact on the results of the etch back process.
Problem 13) Limited options for a barrier material and its deposition method: Changing the deposition process of conductive diffusion barrier layer from the sputter deposition method of poor conformality to a higher conformality counterpart method may be helpful in removing the significant non-uniformity in the effect of the etch back process since the topological characteristics of the more conformal diffusion barrier layer may not change much with changing aspect ratio of the damascene features within a die. Moreover, switching the barrier deposition method for an improved conformality of the conductive diffusion barrier layer is in accordance with the technology trend of which a conductive diffusion barrier of as smallest thickness and highest conformality as possible is required to reduce the volume occupied by the conductive liner layer within a damascene feature. One of such ideal material layers may be a PEALD-grown tantalum carbonitride (can be abbreviated to either TaCN or TaNC) layer of the highest conformality.
However, the prior art damascene processes used for the fabrication of damascene interconnect system having an embedded via (i.e., the punch-through approach) may not be able to adopt any kind of material layer that shows a very high conformality as a conductive diffusion barrier layer. This is because the diffusion barrier layer deposited on the trench bottom 123 (see FIG. 1) can be completely removed by the time when the diffusion barrier layer deposited on the bottom surface 127 of the via is punched through. This is problematic in the case of a damascene process scheme wherein the trench ESL 109 is not deposited in an attempt to decrease an overall dielectric constant of the whole interconnect system. In this situation, any conductor filled into the damascene feature (see FIG. 1) would be leaking through the trench bottom from which the conductive diffusion barrier layer has been removed by the intensive etch back process for forming a recess in the conductor.
Therefore, the prior art damascene processes may have to keep relying on the sputter deposition (PVD) method that deposits a thicker film on the trench bottom than on the bottom surface 127 of the via for the diffusion barrier layer deposition to avoid the damage of the barrier layer on the trench bottom 123, albeit the poor conformality of the as-deposited diffusion barrier may cause aforementioned problems.
The other potential problem of the prior art punch-through approach may arise in selecting a diffusion barrier material. By adopting a conductive diffusion barrier layer of the highest effectiveness, the thickness of the diffusion barrier layer can be maintained as small as possible to comply with the technology trend. This in turn means that the conductive diffusion barrier layer may have to comprise a material of a high bonding force that helps it block other atoms from migrating through it. Note that this high bonding force of a material often makes it more resistant against re-sputtering action used in the punch-through process. The significant problem of the prior art approach for forming the embedded via is, thus, the increasing difficulty in punching the conductive diffusion barrier layer through at the via bottom as the resistance of the barrier material against re-sputtering increases. It means that one may not be able to use very promising conductive diffusion barrier layers, such as a tantalum nitride of a high nitrogen concentration (e.g., PVD-grown TaNy, y>0.1) and the PEALD-grown TaCN layer for the prior art damascene process designed for the fabrication of an interconnect system having an embedded via, if these materials have high resistance against the re-sputtering action of the prior art process.
Providing a promising method that allows the use of the highly conformal and highly efficient conductive barrier layer, regardless of its resistance against the re-sputtering, for the formation of a damascene interconnect system having an embedded via without causing aforementioned problems is within the scope of the present invention.
Problem 14) Loss of an adhesion layer's conductor-grabbing property: Another problem of the prior art damascene process of the punch-through approach may be related to the contamination of the adhesion layer with impurities during its deposition process. FIG. 3C illustrates an adhesion layer 331 deposited over the conductive diffusion barrier layer 311 that has been intensively etched back during the recess formation process step performed as a preparation step for the embedded via fabrication.
Since most of the PVD processes used for material layer growth in prior art damascene processes use highly energetic ion species that usually pick up materials from a layer underlying a growing layer, and deposit the materials in the growing layer, the adhesion layer 331 growing on the conductive diffusion barrier layer 311 that is contaminated with the composite impurity particles 325 can be easily contaminated with the components of the impurity particles.
Since adhesion layers work better when they are in highly pure state in general, the contaminated adhesion layer may not grab or hold the conductor material layer (e.g., Cu seed) overlying it very well. As a consequence, the contaminated adhesion layer can cause the peeling or agglomeration of the conductor layer 334 as illustrated in FIG. 3D.
Once this peeling or agglomeration of the seed layer happened during a damascene process, subsequent conductor deposition by an electrochemical deposition (ECD) process may fail due to the discontinuous electrical path (e.g., peeled or agglomerated Cu seed layer on the contaminated adhesion layer). The contamination of adhesion layer can also be responsible for a fast failure of Cu interconnects during the use of IC devices since the lost or reduced Cu-grabbing power of the adhesion material makes Cu electromigration (EM) happen more easily.
The aforementioned problems can be too severe to be solved by a minor change in the sequence and the parameters of the prior art damascene processes. An example of such a minor sequence change would be found in the prior art approach of Chung et al. (U.S. Application Publication 2005/0106865) in which a conductive diffusion barrier and an adhesion layer are deposited consecutively, followed by the punch-through of these two layers altogether to form a recess at the via bottom, then followed by the deposition of another adhesion layer.